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SCG4000 V3.0 Series Synchronous Clock Generators
PLL
2111 Comprehensive Drive Aurora, Illinois 60505 Phone: 630- 851- 4722 Fax: 630- 851- 5040 www.conwin.com
Application
The Connor-Winfield SCG4000 Series provides high precision phase lock loop frequency translation for the telecommunication applications. SCG4000 Series is well suited for use in line cards, service termination cards and similar functions to provide reliable reference, phase locked, synchronization for TDM, PDH, SONET and SDH network equipment. The SCG4000 Series provides a jitter filtered, wander following output signal sychronized to a superior Stratum or peer input reference signal.
Bulletin Page Revision Date Issued By
Features
* 3.3V High Precision PLL * Tri-State Capability * Active Alarms * Guaranteed Free Run 20ppm * 1 sec. Acquisition Time
SG031 1 of 12 01 30 JULY 02 MBatts
General Description
The SCG4000 Series is a digital phase locked loop generating a LVPECL outputs from an intrinsically low jitter voltage controlled crystal oscillator. The LVPECL outputs may be disabled. The jitter attenuated internal reference, divided down from the output frequency, is also output to a pin. The SCG4000 Series can lock to one of four possible reference frequencies from 8 to 64 kHz, which is selectable using two input select pins. A filtered reference output signal is available at the same frequency. The unit has an acquisition time of about 1 second and it is tolerant of different reference duty cycles. Further features include alarm outputs for Loss-ofReference (LOR) and Loss-of-Lock (LOL). During the LOR alarm, the SCG4000 will also enter a Free Run state, which will guarantee a 20 ppm accurate output. Additionally the Free Run mode may be entered manually. The alarms and reference output may be put into the tri-state high impedance condition for external testing purposes. The maximum package dimensions are 1" x 1.025" x .450" on a 6 layer FR4 board with castellated pins. Parts are assembled using high temperature solder to withstand 63/37 alloy, 180 C surface mount reflow processes.
Functional Block Diagram
Figure 1
SC G 4 000 S e rie s B loc k D iagram
ALARM D ETE C TIO N Force Free R un (P in 13)
LO L Alarm Output (P in 11) LO R Alarm O utput (P in 12)
Q (P in 18) R eference Input (P in 4) D IV ID E R D PFD AN ALO G FILTE R FRE E R U N CO NTROL VCXO Differential LVP E C L Outputs QN (P in 16)
D IV ID E R
Select A (P in 5) Select B (P in 6) VC X O Enable (P in 1)
CM OS Reference Output (P in 7)
Model Comparison Table
Table 1
Model SCG4000 SCG4010 SCG4030 Input Ref Freq 8-64 kHz 19.44 MHz 8-64 kHz Max Duty Cycle 40/60 40/60 45/55 CMOS Reference Output (Pin #7) = Input Ref Freq. 19.44 MHz = Input Ref Freq. LVPECL Oscillator Output (Pin #16 & 18) 125.0 MHz, 155.52 MHz 125.0 MHz, 155.52 MHz 125.0 MHz, 155.52 MHz Tighter Duty Cycle Notes Basic Model
*Features which differentiate a model from the base model (SCG4000) are highlighted in boldface, color and in the notes column.
Data Sheet #: SG031
Page 2 of 16
Rev: 01
Date: 07/30/02
(c) Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Absolute Maximum Rating
Table 2
Symbol Vcc V1 Ts Parameter Power Supply Voltage Input Voltage Storage Temperature
All SCG4000 Models
Minimum 3.0 -0.5 -65 Nominal Maximum 3.6 5.5 150 Units Volts Volts deg. C Notes
Operating Specifications
Table 3
Symbol Vcc Icc To Ffr Fcap Fbw Tjtol Taq Trf Parameter Power Supply Voltage Power Supply Current Temperature Range Free Run Accuracy Capture/pull-in range Jitter Filter Bandwidth Input Jitter Tolerance Acquisition Time Output Rise and Fall Time (20% 80%)
All SCG4000 Models
Minimum 3.135 0 -20 -25 100 Nominal 3.3 230 1 225 Maximum 3.465 280 70 20 25 10 31.25 1.0 350 Units Volts mA C ppm ppm Hz s s s ps SCG4000, SCG4030 SCG4010 2.0 3.0 Notes 1.0
Features
Table 4
Parameter Alarms TDEV MTIE Static Offset Dynamic Offset VCXO Output Logic Type Reference Output Logic Type Package
All SCG4000 Models
Specifications LOR, LOL Status on seperate CMOS Outputs 70 ps (typical) 800 ps (typical) 26 ns Maximum 20 ns Maximum LVPECL CMOS FR4 SM 1.0" x 1.025" x 0.45" 4.0 5.0 Notes
CMOS Input And Output Characteristics
Table 5
Symbol VIH VIL TIO CO VHO VIO TIR
NOTES: 1.0: 2.0: 3.0: 4.0: 5.0:
All SCG4000 Models
Parameter High Level Input Voltage Low Level Input Voltage I/O to Output Valid Output Capacitance High Level Output Voltage loh = 04mA Low Level Output Voltage lo1 = 8mA Input Reference Signal Pulse Width 12.5 2.4 0.4 nS Minimum 2 0 Nominal Maximum 5.5 0.8 10 10 Units V V nS pF Vcc Min. Vcc Max. Notes
Requires external regulation and filter (22uF, 330 pF) From a 20 ppm offset in reference frequency 50 load biased to 1.3V Offset between Reference Input and Reference Output @ room temp. Offset change between Reference Input and Reference Output over temperature range from room temperature.
Data Sheet #: SG031
(c) Copyright 2002 The Connor-Winfield Corp.
Page 3 of 16
Rev: 01
Date: 07/30/02
All Rights Reserved Specifications subject to change without notice
LVPECL Output Characteristics
Table 6
Symbol VOH VOL CL TSKEW Parameter High Level PECL Voltage Low Level PECL Voltage Output Capacitance Differential Output Skew 50
All SCG4000 Models
Minimum 2.27 1.49 Nominal 2.34 1.51 Maximum 2.42 1.68 10 Units V V pF ps Notes
Output Jitter Specifications
Table 7
Frequency (MHz) 125.00 155.52 pS (RMS) 6(typical) 6(typical)
All SCG4000 Models
Jitter BW 10 Hz - 20 MHz m UI 0.750 (typical) 0.933 (typical) SONET Jitter BW 12 kHz - 20 MHz pS (RMS) 1 (max), 0.3 (typical) 1 (max), 0.4 (typical) m UI 0.125(max) 0.156 (max)
Output Programming
Table 8
Tristate 0 1 0 0 X 1
Alarm Status
Table 9
0 1 X 0 0 1
All SCG4000 Models
Free Run Output Locked to reference selected (default) Hi-Z Tristate condition Free run at nominal frequency
All SCG4000 Models
Alarm Output No alarm Loss-of-Lock Loss-of-Reference
LOL Output LOR Output
Pin Description
Table 10
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Connection Enable/Disable TCK TDO Reference In Select A Select B Reference Out Ground Tri-State Enable VCC Loss of Lock Loss of Reference Free Run TDI TMS VCXO Out Signal Ground VCXO Out
All SCG4000 Models
Description Enable = 0, Disable = 1 for VCXO Ouputs, Default = 0 (for No Connect) JTAG pin that is used only by Connor-Winfield for programming. Do not connect JTAG pin that is used only by Connor-Winfield for programming. Do not connect CMOS Reference Frequency Input Reference Frequency Select Pin, Default = 0 (for No Connect) Reference Frequency Select Pin, Default = 0 (for No Connect) Filtered Reference Output Power Ground CMOS Output Tri-State enable (Hi-Z =1, Default = 0) 3.3V Supply Voltage. LOL Alarm Output LOR Alarm Output Force output frequency to Free Run (FR = 1, Default = 0) JTAG pin that is used only by Connor-Winfield for programming. Do not connect JTAG pin that is used only by Connor-Winfield for programming. Do not connect VCXO differential LVPECL Output VCXO output ground (Shield) VCXO differential LVPECL Output
Data Sheet #: SG031
Page 4 of 16
Rev: 01
Date: 07/30/02
(c) Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Maximum Package Dimensions
Figure 2
Recommended Footprint and Keepout Area Dimensions
Figure 3
Keep Out Area
Data Sheet #: SG031
(c) Copyright 2002 The Connor-Winfield Corp.
Page 5 of 16
Rev: 01
Date: 07/30/02
All Rights Reserved Specifications subject to change without notice
Tape and Reel Dimensions
Figure 4
Solder Profile
Figure 5
250
200
Temp (C)
150
100
50
0
1
2
3
4
5
6
Time(minutes) Recommended Reflow Profile
Peak Temp:217C MaxRiseSlope:1.5 C/Sec Time Above150C:100Sec
Data Sheet #: SG031
Page 6 of 16
Rev: 01
Date: 07/30/02
(c) Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Typical Application
Figure 6
Typical Application of Connor-Winfield's SCG4000 Series Timing Products
BITS System Signal
Line Cards
Input Select
Timing Card #1
A CW's STM/MSTM module A MUX B C MUX S Y B Y S CW's SCG 4000
Clock out
RCV
Timing Card #2
A CW's STM/MSTM module S A MUX B MUX S Y Y CW's SCG 4000 Clock out
B C
RCV
System Select
Typical System Test Set-up
Figure 7
This device supplies system time information. It can be thought of as supplying "absolute time" reference information GPS or LORAN Timing Source
Sample M T IE D a ta fo r ST M -S 3/M ST M - S3
10 MHz
M TIE (s
Possible Choices Include Stanford Research Model: FS700 Truetime Model XXX
1.0E-6
T ypical respo nse - 3000 seco nd tes t - Jitter applied (2 UI @ 10 H z) re f date AP R 22 1998 kdh
100.0E-9
10.0E-9
MTIE 1244-5.2 Mas k (A ) 1244-5.2 Mas k (B) 1244-5.6 Mas k G R253-5. 4. 4. 3.2
1.0E-9 100 .0E- 3
1.0E+0
10.0E+0
10 0.0E+0
1.0E+3
10.0 E+3
Obs erva tion Tim e (s )
C o pyright 1998 Co nno r-Winfield a ll righ ts reserv ed
Target System Under Test
External Reference Input
Arbitrary Waveform Generator
DS1 rate RZ (1.544 MHz), E1 rate RZ or 8 kHz clock RZ with noise modulation
Clock or BITS logic level clock input (TTL, CMOS, etc.)
Standards Compliance Documents MTIE, TDEV, Wander Transfer, and Wander Generation Plots OC-12 Line Card OC-48 Line Card OC-3 Line Card DS-1 Line Card Timing Card Timing Card Line Card
Sample Wande r G e ne ra tion ( T D EV) for S T M /M ST M -S 3
1.0E - 6
Noise Modulation Input
Typ ical respo nse - 300 sec ond test - Jitter applied (2 UI @ 10 Hz) 0 ref date A PR 22 1998 kdh
10 MHz
10 0.0E - 9
. . . . ...
1 0.0E - 9
TDEV (se c
TDEV
1.0E - 9
G R1244-Fig5.1 G R1244-Fig5-3
External Reference Input
Arbitrary Waveform Generator [Noise Source]
100 .0E - 12 1 0.0E - 3
100.0E- 3
1.0E +0
10.0E +0
100.0E +0
1.0E + 3
Inte g r atio n Time (s e c)
C o pyright 1998 Co nno r-W infield a lll rights re served
DS1 rate [1.544 MHz] BITS Bipolar DS-1, OC-3, OC-12 electrical or optical signals 10 MHz Tektronix SJ300E
10 MHz
Time-stamped ensemble based on absolute time reference (10MHz input) Phase Error data output
External Reference Input
HP53310A Modulation Analyzer / Time Interval Analyzer
Wander Analyzer data (IEEE-488)
External Reference Input
TEKTRONIX SJ300E
IEEE-488 Controller Platform for software HP 53305A Phase Analyzer HP E1748A Sync Measurement Tektronix Wander Analyzer
Data Sheet #: SG031
(c) Copyright 2002 The Connor-Winfield Corp.
Page 7 of 16
Rev: 01
Date: 07/30/02
All Rights Reserved Specifications subject to change without notice
Alarm Timing Diagram
Figure 8
LOR Output
Start-up Region
4
LOL Output 2 3
Phase Detector
1
1
External Reference
Internal Reference 2 LOR Output 2 2 2 2 2 2 2 2 2 2 2 2 2
LOL Output
5
Phase Detector
1
1 3 3
1
1
1
External Reference
Internal Reference 2 2 2 2 2 2 2 2 2 2 2 2 2 2
1 2 3 4 5
Start-up Region
19.44 MHz &77.76 MHz Reference Input Units < 1 sec 1 sec > 1 sec LOR is active when LOL is active Minimum pulse width = 2 sec
8 kHz Reference Input Units < 31.25 sec 31.25 sec > 31.25 sec 125 sec wide range Minimum pulse width = 62.5 sec
During Start-up, The LOL Alarm will pulse during the first second of operation
Data Sheet #: SG031
Page 8 of 16
Rev: 01
Date: 07/30/02
(c) Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
SCG4000 Series Typical MTIE
Figure 9
1 .0 E -9
1 0 0 .0 E -1 2 1 .0 E -3
MTIE
1 0 .0 E -3
1 0 0 .0 E -3
1 .0 E + 0
1 0 .0 E + 0
1 0 0 .0 E + 0
O b s e rv a tio n W in d o w (T a u )
SCG4000 Series Typical TDEV
Figure 10
1 0 0 .0 E -1 2
1 0 .0 E -1 2 1 .0 E -3
TDEV
1 0 .0 E -3
1 0 0 .0 E -3 Tau
1 .0 E +0
1 0 .0 E + 0
Data Sheet #: SG031
(c) Copyright 2002 The Connor-Winfield Corp.
Page 9 of 16
Rev: 01
Date: 07/30/02
All Rights Reserved Specifications subject to change without notice
SCG4000 SCG4000 Individual Features:
* Four selectable References: 8, 16, 32, and 64 kHz. * LVPECL Oscillator Output: 125.0 MHz or 155.52 MHz * CMOS reference output frequency equals input reference frequency. The SCG4000 is Connor-Winfield's base model for the SCG4000 Series product line. The SCG4000 can lock to one of four input reference frequencies from 8 to 64 kHz which is selectable using two input control pins.
Input Reference Selection
Table 11
Input Sel A (Pin #5) 0 1 0 1
SCG4000
Input Sel B (Pin #6) 0 0 1 1 Reference Frequency (Pin #8) 8 kHz (default) 16 kHz 32 kHz 64 kHz
Reference and Output Availability
Table 12
Input Reference (Pin #4) 8 kHz 8 kHz 16 kHz 32 kHz 64 kHz
SCG4000
LVPECL Oscillator Output (Pin #16 & #18) 125.0 MHz 155.52 MHz CMOS Reference Output (Pin #7) 8 kHz 8 kHz 16 kHz 32 kHz 64 kHz
Ordering Information
SCG4000-125.0M SCG4000-155.52M
Data Sheet #: SG031
Page 10 of 16
Rev: 01
Date: 07/30/02
(c) Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
SCG4010 SCG4010 Individual Features:
* Input Reference: 19.44 MHz * LVPECL Oscillator Output: 125.0 MHZ or 155.52 MHz * CMOS Reference Output: 19.44 MHz The SCG4010 only accepts a 19.44 MHz input while providing a phase locked LVPECL output. Also provided is a phase locked 19.44 MHz CMOS reference output.
Input Reference Selection
Table 13
Input Sel A (Pin #5) X
Note: X= Don't Care
SCG4010
Input Sel B (Pin #6) X Reference Frequency (Pin #8) 19.44 MHz (default)
Reference and Output Availability
Table 14
Input Reference (Pin #4) 19.44 MHz
SCG4010
LVPECL Oscillator Output (Pin #16 & #18) 125.0 MHz, 155.52 MHz CMOS Reference Output (Pin #7) 19.44 MHz
Ordering Information
SCG4010-125.0M SCG4010-155.52M
Data Sheet #: SG031
(c) Copyright 2002 The Connor-Winfield Corp.
Page 11 of 16
Rev: 01
Date: 07/30/02
All Rights Reserved Specifications subject to change without notice
SCG4030 SCG4030 Individual Features:
* Four selectable References: 8, 16, 32, and 64 kHz. * 45/55 Duty cycle * LVPECL Oscillator Output: 125.0MHz or 155.52 MHz * CMOS reference output frequency equals input reference frequency. The SCG 4030 is similar to the SCG4000 except the SCG4030 offers a duty cycle of 45/ 55 for applications that require a tighter duty cycle. The SCG4030 can lock to one of four input reference frequencies from 8 to 64 kHz which is selectable using two input control pins.
Input Reference Selection
Table 15
Input Sel A (Pin #5) 0 1 0 1
SCG4030
Input Sel B (Pin #6) 0 0 1 1 Reference Frequency (Pin #8) 8 kHz (default) 16 kHz 32 kHz 64 kHz
Reference and Output Availability
Table 16
Input Reference (Pin #4) 8 kHz 8 kHz 16 kHz 32 kHz 64 kHz
SCG4030
LVPECL Oscillator Output (Pin #16 & #18) 125.0 MHz 155.52 MHz CMOS Reference Output (Pin #7) 8 kHz 8 kHz 16 kHz 32 kHz 64 kHz
Ordering Information
SCG4030-125.0M SCG4030-155.52M
Data Sheet #: SG031
Page 12 of 16
Rev: 01
Date: 07/30/02
(c) Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Data Sheet #: SG031
(c) Copyright 2002 The Connor-Winfield Corp.
Page 13 of 16
Rev: 01
Date: 07/30/02
All Rights Reserved Specifications subject to change without notice
Data Sheet #: SG031
Page 14 of 16
Rev: 01
Date: 07/30/02
(c) Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Data Sheet #: SG031
(c) Copyright 2002 The Connor-Winfield Corp.
Page 15 of 16
Rev: 01
Date: 07/30/02
All Rights Reserved Specifications subject to change without notice
2111 Comprehensive Drive Aurora, Illinois 60505 Phone: 630- 851- 4722 Fax: 630- 851- 5040 www.conwin.com
Revision 00 01
Revision Date 6/14/02 7/30/02
Note Final Product Release Advanced to V3.0

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